On testing of non-isolated embedded legacy cores and their surrounding logic

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 41-48

  Pomeranz, Irith ^a   Zorian, Yervant ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; ERROR DETECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MODELS; VECTORS;

EMBEDDED LEGACY CORES; FAULT COVERAGE; PARTIAL ISOLATION RING; USER DEFINED LOGIC;

LOGIC CIRCUITS;

EID: 0032644942     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)