Improved delay prediction for on-chip buses

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 497-501

  Pomerleau, Real G ^a   Franzon, Paul D ^a   Bilbro, Griff L ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; TREES (MATHEMATICS);

HIGH-LEVEL SYNTHESIS; ON-CHIP BUSES; WIRING DELAY;

INTERCONNECTION NETWORKS;

EID: 0032640862     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309986     Document Type: Conference Paper

References (12)