Design and implementation of dynamic load balancing algorithms for rollback reduction in optimistic PDES

VLSI Design

Volumn 9, Issue 3, 1999, Pages 271-290

  Sarkar, Falguni ^a,b,c   Das, Sajal K ^a,d,e  

^a UNIVERSITY OF NORTH TEXAS   (United States)

^b NORTEL NETWORKS   (United States)

^c INDIAN STATISTICAL INSTITUTE   (India)

^d UNIVERSITY OF CALCUTTA   (India)

^e UNIVERSITY OF CENTRAL FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; COMPUTER WORKSTATIONS; GENETIC ALGORITHMS; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

DYNAMIC LOAD BALANCING; LOAD TRANSFER; PARALLEL DISCRETE EVENT SIMULATION; PROCESS MIGRATION; TIME WARP;

LOGIC DESIGN;

EID: 0032638678     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1999/64750     Document Type: Article

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