A new bare die test methodology

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 290-295

  Yang, Zao ^a   Cheng, K T ^a   Tai, K L ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; INTEGRATED CIRCUITS; MULTICHIP MODULES; RANDOM ACCESS STORAGE; RELIABILITY; YIELD STRESS;

BARE DIES; PRESSURE CONTACT TECHNOLOGY; TESTER ON A CHIP;

INTEGRATED CIRCUIT TESTING;

EID: 0032638328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vtest.1999.766678     Document Type: Article

References (22)