A distributed deadlock resolution algorithm for the AND model

IEEE Transactions on Parallel and Distributed Systems

Volumn 10, Issue 5, 1999, Pages 433-447

  González De Mendívil, José Ramón ^a,b   Fariña, Federico ^b   Garitagoitia, José Ramón ^b   Alastruey, Carlos F ^b   Bernabeu Auban, J M ^a,c  

^a IEEE   (Spain)

^b PUBLIC UNIVERSITY OF NAVARRE   (Spain)

^c UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

AND model; Deadlock detection resolution; Distributed systems; Hierarchical correctness proofs; Input output automata model

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; COMPUTER SYSTEMS PROGRAMMING; DISTRIBUTED COMPUTER SYSTEMS; FORMAL LOGIC; MATHEMATICAL MODELS; THEOREM PROVING;

DISTRIBUTED DEADLOCK RESOLUTION ALGORITHMS; HIERARCHICAL CORRECTION PROOF; INPUT/OUTPUT AUTOMATA MODELS;

COMPUTER SYSTEM RECOVERY;

EID: 0032637097     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.770131     Document Type: Article

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