An output encoding problem and a solution technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 6, 1999, Pages 761-768

  Mitra, Subhasish ^a,b,c   Avra, Lanae J ^a   McCluskey, Edward J ^a  

^a IEEE   (United States)

^b Stanford University   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Built in self test (bist); Column compaction; Encoding; Network flow problem; One hot signal; Scan

Indexed keywords

ALGORITHMS; BINARY CODES; ENCODING (SYMBOLS); FINITE AUTOMATA; PROBLEM SOLVING; SEQUENTIAL MACHINES;

COLUMN COMPACTION; OUTPUT ENCODING PROBLEMS;

BUILT-IN SELF TEST;

EID: 0032636544     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.766726     Document Type: Article

References (16)

1. P. Ashar, S. Devadas, and A. R. Newton, Sequential Logic Synthesis. Norwell, MA: Kluwer Academic, 1991.
2. D. Binger and D. W. Knapp, "Encoding multiple outputs for improved column compaction," in Proc. ICCAD-91. 1991, pp. 230-233.
3. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms.Cambridge, MA; The MIT Press, and New York: McGraw Hill, 1989.
4. G. De Micheli, R. Brayton, and A. Sangiovanni-Vincentelli, "KISS: A program for optimal state assignment of finite state machines," in Proc. ICC AD, 1984, pp. 209-211.
5. S. Devadas and A. R. Newton, "Exact algorithms for output encoding, state assignment and four level boolean minimization," IEEE Trans. Computer-Aided Design, vol. 10, pp. 13-27, Jan. 1991.
6. L. R. Ford and D. R. Fulkerson, Flows in Networks. Princeton, NJ: Princeton Univ., 1962.
7. G10-p Cell-Based ASIC Products Databook, LSI Logic, May 1996.
8. E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1986.
9. S. Mitra, L. J. Avra, and E. J. McCluskey, "Scan synthesis for one-hot signals," in Proc. Int. Test Conf., 1997, pp. 714-722.
10. _, "An output encoding problem and a solution technique," in Proc. ICC AD-97, 1997, pp. 304-307.
11. A. Saldanha and R. H. Katz, "PLA optimization using output encoding," in Proc. ICCAD-88, 1988, pp. 478-181.
12. E. Sentovich et al., "SIS: A system for sequential circuit synthesis," Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, Electronics Res. Lab. Memo. no. UCB/ERL M92/41,
13. T. Villa and A. Sangiovanni-Vincentelli, "NOVA: State assignment of finite state machines for optimal two-level logic implementation," IEEE Trans. Computer-Aided Design, vol. 9, pp. 905-924, Sept. 1990.
14. R. Wei and C. Tseng, "Column compaction and its application to the control path synthesis," in Proc. ICC AD-87, 1987, pp. 320-323.
15. S. Yang and M. J. Ciesielski, "Optimum and suboptimum algorithms for input encoding and its relation to logic minimization," IEEE Trans. Computer-Aided Design, vol. 10, pp. 4-12, Jan. 1991.
16. S. Mitra, L. J. Avra, and E. J. McCluskey, "An output encoding problem and a solution Technique," Center for Reliable Computing, Stanford Univ., Stanford, CA, Tech. Rep. CRC TR 99-1. [Online]. Available: http://www-crc.stanford.edu.