Design of a novel delayed LMS decision feedback equalizer for HIPERLAN/1 FPGA implementation

IEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall

Volumn 1, Issue , 1999, Pages 300-304

  Sun, Y ^a   Nix, A R ^a   Bull, D R ^a   Milford, D ^a   de Beauchesne, H ^a   Sperling, R ^a   Rouzet, Ph ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION FEEDBACK EQUALIZER (DFE); DELAYED LEAST MEAN SQUARE (DLMS);

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; MODULATION;

EQUALIZERS;

EID: 0032634528     PISSN: 07400551     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (4)