A general interprocedural framework for placement of split-phase large latency operations

IEEE Transactions on Parallel and Distributed Systems

Volumn 10, Issue 4, 1999, Pages 394-413

  Agrawal, Gagan ^a  

^a University of Delaware   (United States)

Author keywords

Code motion; Data flow analysis; Input output; Interprocedural analysis; Memory hierarchy transformations

Indexed keywords

DATA FLOW ANALYSIS; HIERARCHICAL SYSTEMS; PARALLEL PROCESSING SYSTEMS;

INTERPROCEDURAL ANALYSIS; MEMORY HIERARCHY TRANSFORMATIONS;

COMPUTER ARCHITECTURE;

EID: 0032630999     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.762818     Document Type: Article

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