Analogue multilayer perceptron circuit with on-chip training

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 1999, Pages

  Foruzandeh, B ^a   Quigley, S F ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG MULTILAYER PERCEPTRON (MLP) CIRCUITS; ON-CHIP CONTROL CIRCUITS;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; FEEDFORWARD NEURAL NETWORKS; LEARNING SYSTEMS; MICROPROCESSOR CHIPS; PERTURBATION TECHNIQUES; VLSI CIRCUITS;

MULTILAYER NEURAL NETWORKS;

EID: 0032630855     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (5)

1. J. B. Lont, Walter Guggenbuhl, Analogue CMOS Implementation of a Multilayer Perceptron with Nonlinear Synapses, IEEE Trans. Neural Networks, Vol.3, No.3, pp. 475-464, May 1992.
2. M. Jabri, B. Flower, Weight Perturbation: An Optimal Architecture and Learning Technique for Analogue VLSI Feedforward and Recurrent Multilayer Networks, IEEE Trans. Neural Networks, Vol.3, No.l, January 1992.
3. K. Bult, H. Wallinga, A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation, Journal of Solid-State Circuits, Vol. SC-22, No. 3, pp. 357-365, June 1987.
4. C. Toumazou, F. J. Lidgey & D. G. Haigh, Analogue IC Design: the current-mode approach, IEE Circuits and Systems, Series 2, Published by: Peter Peregrinus Ltd., on behalf of the Institution of Electrical Engineers, London, 1990.
5. C. A. Mead, T. Delbruck, Scanners for Visualizing Activity of Analog VLSI Circuitry, Analog Integrated Circuits and Signal Processing 1, Kluwer Academic Publishers, Boston, pp. 93-106, 1991.