Low-power parallel video compression architecture for a single-chip digital CMOS camera

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 21, Issue 3, 1999, Pages 195-207

  Hsieh, Jeff Y F ^a   Meng, Teresa H Y ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAMERAS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; IMAGE COMPRESSION; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE;

PARALLEL VIDEO COMPRESSION ARCHITECTURE; SINGLE CHIP DIGITAL CMOS CAMERA;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032629255     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008006400249     Document Type: Article

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