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Volumn 46, Issue 5, 1999, Pages 637-640

An improved refinable rational approximation to the ideal time delay

Author keywords

Approximation; Bessel approximation; E tds; Ideal time delay; Pad

Indexed keywords

APPROXIMATION THEORY; CONTROL SYSTEM SYNTHESIS; ELECTRIC NETWORK SYNTHESIS; ERRORS; LAPLACE TRANSFORMS; STEP RESPONSE; TRANSFER FUNCTIONS;

EID: 0032627269     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.762930     Document Type: Article
Times cited : (36)

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  • 2
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    • S. Lin and E. S. Kuh, "Circuit simulation for large interconnected IC networks," in Proc. IFIP Int. Conf. VLSI, Sept. 1993, pp. 333-342.
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  • 9
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    • Synthesis of constant-time delay ladder networks using Bessel polynomials
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  • 10
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.