Chaotic generation of PN sequences: A VLSI implementation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 1999, Pages

  Dornbusch, Andrew ^a   Pineda de Gyvez, Jose ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY PSEUDO-NOISE (PN) SEQUENCES; COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD);

CHAOS THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CORRELATION METHODS; DIFFERENCE EQUATIONS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; LOGIC DEVICES; RANDOM PROCESSES; VLSI CIRCUITS;

SPURIOUS SIGNAL NOISE;

EID: 0032626816     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)

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10. K.R. Laker, W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, New York, 1994