Minimal-connectivity circuit for analogue sorting

IEE Proceedings: Circuits, Devices and Systems

Volumn 146, Issue 3, 1999, Pages 108-110

  Rovetta, S ^a   Zunino, R ^a  

^a UNIVERSITY OF GENOA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LEARNING SYSTEMS; NEURAL NETWORKS; SORTING; VLSI CIRCUITS;

ANALOG SORTING;

CMOS INTEGRATED CIRCUITS;

EID: 0032623386     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19990323     Document Type: Article

References (8)

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3. URAHAMA, K., and NAGAO, T.: 'Direct analog rank filtering', IEEE Trans. Circuits and Syst. I. Fundam. Tlieory and Appl, 1995,42, (7), pp. 385-388
4. DEMOSTHENOUS, A., SMEDLEY, S., and TAYLOR.J.: 'A CMOS analog \vinner-take-all network for large-scale applications', IEEE Trans. Circuits Syst. I, Fundam. Tlieory and Appl, 1998, 45, (3), pp. 300-304
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7. SANCHEZ-SINENCIO, E., and GUNAY, Z.S.: 'CMOS winnertake-all circuits: a detail comparison'. Proceedings of ISCAS'97, Hong Kong, 1997, Vol. 1, pp. 41-44
8. ANCONA, F., ODDONE, G., ROVETTA, S., UNEDDU, G., and ZUNINO, R.: 'A vector quantization circuit for trainable neural networks'. Proceedings of 3rd international conference on Electr. circuits and systems, ICECS'96, Rodos, 1996, Vol. 2, pp. 1131-1134