Scability of fully-depleted SOI technology into 0.13 μm 1.2 V-1 V CMOS generation

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 86-87

  Raynaud, C ^a   Faynot, O ^a   Pelloie, J L ^a   Martin, F ^a   Tedesco, S ^a   Cluzel, J ^a   Grouillet, A ^a   Dal'zotto, B ^a   Vanhoenacker, D ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SEMICONDUCTING SILICON COMPOUNDS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

PARTIALLY DEPLETED (PD) DEVICES; TITANIUM SILICIDE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0032608151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)