TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1999, Pages 159-162

  Makris, Yiorgos ^a   Collins, Jamison ^a   Orailoglu, Alex ^a   Vishakantaiah, Praveen ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST FOURIER TRANSFORMS; LOGIC CIRCUITS; LOGIC DESIGN; SHIFT REGISTERS; VECTORS;

CHANNEL TRANSPARENCY; HIERARCHICAL TEST GENERATION; MODULE REACHABILITY PATHS; REGISTER TRANSFER LEVEL; TESTABILITY ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0032597868     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)