Clock verification in the presence of IR-drop in the power distribution network

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1999, Pages 437-440

  Hussain, Syed Zakir ^a   Rochel, Steffen ^a   Overhauser, David ^a   Saleh, Resve ^a  

^a Simplex Solutions Inc

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC DESIGN; LOGIC GATES; VLSI CIRCUITS;

CLOCK CIRCUITRY; CLOCK VERIFICATION;

TIMING CIRCUITS;

EID: 0032597775     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)