A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's

IEEE Transactions on Electron Devices

Volumn 46, Issue 9, 1999, Pages 1877-1882

  Wang, Tahui ^a,b   Chiang, Lu Ping ^b   Zous, Nian Kai ^b   Hsu, Charng Feng ^b   Huang, Li Yuan ^b   Chao, Tien Sheng ^c  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c National Nano Laboratories   (Taiwan)

Author keywords

Drain leakage degradation; Hot carrier; Thin oxide

Indexed keywords

ELECTRIC CHARGE; ELECTRIC POTENTIAL; HOT CARRIERS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; OXIDES;

CHARGE SEQUENTIAL TUNNELING CURRENTS; HOT CARRIER INDUCED DRAIN LEAKAGE CURRENT DEGRADATION; SHOCKLEY-READ-HALL GENERATION CURRENT;

MOSFET DEVICES;

EID: 0032595345     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.784188     Document Type: Article

References (16)

1. J. Chen, T. Y. Chan, P. K. Ko, and C. Hu, "Subbreakdown drain leakage current in MOSFET," IEEE Electron Device Lett., vol. EDL-8, pp. 515-517, 1987.
2. S. Eto et al., "A 1Gb SDRAM with ground level prechargea bitline and nonboosted 2.1V wordline," in ISSCC Tech. Dig., 1998, pp. 82-83.
3. H. Suzuki, M. Kojima, and Y. Nara, "Trap assisted leakage mechanism of 'worst' junction in giga-bit DRAM using negative word-line voltage," SSDM Ext. Abstr., pp. 32-33, 1998.
4. C. Hu, S. C. Tam, F. Hsu, P. Kuo, T. Chan, and K. W. Terrill, "Hot electron induced MOSFET degradation - model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED-32, pp. 375-385, Feb. 1985.
5. M. Yoshida, D. Tohyama, K. Maeguchi, and K. Kanzaki, "Increase of resistance to hot carriers in thin oxide MOSFET's," in IEDM Tech. Dig., 1985, pp. 254-257.
6. T. Wang, C. Hung, P. C. Chou, S. S. Chung, and T. E. Chang, "Effects of hot carrier induced interface state generation in submicron LDD MOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 1618-1622, 1994.
7. H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, "A study of hot carrier degradation in n- and p-MOSFET's with ultra-thin gate oxides in the direct tunneling regime," in IEDM Tech. Dig., 1997, pp. 453-456.
8. H. Sasaki, M. Saitoh, and K. Hashimoto, "Hot-carrier induced drain leakage current in n-channel MOSFET," in IEDM Tech. Dig., 1987, pp. 726-729.
9. T. Wang, T. E. Chang, and C. Hung, "Interface trap induced thermionic and field emission current in off-state MOSFET's," in IEDM Tech. Dig., 1994, pp. 161-164.
10. A. Frommer, M. R. Pinto, and J. D. Bude, "Two-stage leakage degradation in submicro MOSFET technology," in Symp. VLSI Technology, 1996, pp. 164-165.
11. C. T. Wang, Hot Carrier Design Consideration for MOS Devices and Circuits. New York: Van Nostrand Reinhold, 1992, ch. 2.
12. "TMA MEDICI: Two-dimensional Device Simulation Program," Technology Modeling Associates, Inc., 1992.
13. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling," in IEDM Tech. Dig., 1987, pp. 721-724.
14. S. M. Sze, Semiconductor Device Physics and Technology. New York: Wiley, 1985.
15. d) during hot-carrier stressing of n-MOS transistors," IEEE Trans. Electron Devices, vol. 37, pp. 744-754, Mar. 1990.
16. R. Troutman, "VLSI limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices, vol. ED-26, pp. 461-469, 1979.