Trade-off between operational speed and error occurrence for single electron circuits on the quantum scale

Microelectronic Engineering

Volumn 47, Issue 1, 1999, Pages 269-271

  Usuki, Tatsuya ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; ERRORS; LOGIC CIRCUITS; LOGIC DESIGN; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE; SHIFT REGISTERS;

LANDAU-ZENER TUNNELING PROCESS; QUANTUM SCALE; SINGLE ELECTRON CIRCUITS;

SEMICONDUCTOR QUANTUM DOTS;

EID: 0032594680     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(99)00211-7     Document Type: Article

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