CMOS trimming circuit based on polysilicon fusing

Electronics Letters

Volumn 34, Issue 4, 1998, Pages 355-356

  Kim, O ^a   Oh, C J ^a   Kim, K S ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FUSES; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; SEMICONDUCTING SILICON;

TRIMMING CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0032545827     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980320     Document Type: Article

References (4)

1. VYNE, R.L., DAVIS, W.F., and SUSAK, D.M.: 'A monolithic p-channel JFET quad op amp with in-package trim and enhanced gainbandwidth product', IEEE J. Solid-State Circuits, 1987, SSC-22, (6), pp. 1130-1138
2. AMEMIYA, Y., ONO, T., and KATO, K.: 'Electrical trimming of heavily doped polycrystalline silicon resistors', IEEE Trans. Educ., 1979, 26, (11), pp. 1738-1742
3. KOLLURI, M.: 'A 12b 500ns subranging ADC'. Intl. Solid State Circuit Conf., San Francisco, USA, 1989, pp. 18-19
4. KIM, O., OH, C., KWON, J., LEE, J., SONG, Q., SONG, W., KIM, K., and PARK, H.: 'A CMOS implementation of CDMA/FM IF signal processor'. Symp. VLSI Circuits, Kyoto, Japan, 1997, pp. 115-116