Transconductance enhancement at low temperatures in deep submicrometre MOSFETs

Electronics Letters

Volumn 34, Issue 18, 1998, Pages 1793-1794

  Szelag, B ^a   Balestra, F ^a  

^a Grenoble INP Phelma   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FERMI LEVEL; LOW TEMPERATURE OPERATIONS; SEMICONDUCTING SILICON; TRANSCONDUCTANCE;

QUASI-FERMI POTENTIAL GRADIENT;

MOSFET DEVICES;

EID: 0032480194     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981227     Document Type: Article

References (5)

1. Special issue of IEEE Trans. Electron Devices on Low Temperature Electronics, ED-36, 1989
2. BALESTRA, F., and GHIBAUDO, G.: 'Brief review of MOS device physics for low temperature electronics', Solid-State Electron., 1994, 37, p. 1967
3. GUO, J.C., CHANG, M.C., LU, C.Y., HSU, C., and CHUNG, S.: 'Transconductance enhancement due to back bias for submicron NMOSFET', IEEE Trans. Electron Devices, 1995, ED-42, p. 288
4. 'Atlas', Version 4.0 (SILVACO international, 1996)
5. NGUYEN-DUC, CH., CRISTOLOVEANU, S., and GHIBAUDO, G.: 'Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance', Solid-State Electron., 1986, 29, p. 1271