Self-timed boundary-scan cells for multi-chip module test

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 92-97

  Garcia, T A ^a   Acosta, A J ^a   Mora, J M ^a   Ramos, J ^a   Huertas, J L ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; DIGITAL CIRCUITS; ELECTRIC FAULT LOCATION; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0032320717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)