6-μ m2 bipolar transistor using 0.25-μ m process technology for high-speed applications

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 1998, Pages 152-155

  Hashimoto, T ^a   Kikuchi, T ^a   Watanabe, K ^a   Wada, S ^a   Tamaki, Y ^a   Kondo, M ^a   Natsuaki, N ^a   Owada, N ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CAPACITANCE; INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; LITHOGRAPHY; SEMICONDUCTOR JUNCTIONS; ULSI CIRCUITS;

PARASITIC CAPACITANCE;

BIPOLAR TRANSISTORS;

EID: 0032320191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)