Waiting false path analysis of sequential logic circuits for performance optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 392-395

  Nakamura, Kazuhiro ^a   Takagi, Kazuyoshi ^a   Kimura, Shinji ^a   Watanabe, Katsumasa ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED LOGIC DESIGN; DECISION THEORY; LOGIC GATES; OPTIMIZATION;

FALSE PATH ANALYSIS;

SEQUENTIAL CIRCUITS;

EID: 0032318394     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.289059     Document Type: Conference Paper

References (8)