Current path optimized structure for high drain current density and high gate-turn-on voltage enhancement mode heterostructure field effect transistors

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 1998, Pages 198-201

  Hara, Naoki ^a   Nakasha, Yasuhiro ^a   Nagahara, Masaki ^a   Joshin, Kazukiyo ^a   Watanabe, Yuu ^a   Takikawa, Masahiko ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION; POWER AMPLIFIERS; SEMICONDUCTOR DEVICE STRUCTURES;

CURRENT PATH OPTIMIZED STRUCTURE;

JUNCTION GATE FIELD EFFECT TRANSISTORS;

EID: 0032318331     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)