Effect of body-to-source bias on the analog characteristics of 0.35 μm partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

IEEE International SOI Conference

Volumn , Issue , 1998, Pages 25-26

  Babcock, Jeffrey A ^a   Francis, Pascale ^a   Haggag, Hosam ^a   Darmawan, Johan ^a   Lee, Tsung Wen ^a   Lindorfer, Philipp ^a   Olgaard, Christian ^a   Merrill, Richard B ^a   Schroder, Dieter K ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; THRESHOLD VOLTAGE;

BODY-TO-SOURCE VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0032317484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)