Applying Built-In Self-Test to majority voting fault tolerant circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 303-308

  Stroud, Ch E ^a   Tannehill, J K ^a  

^a UNIVERSITY OF KENTUCKY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; EFFICIENCY; LOGIC CIRCUITS; RANDOM PROCESSES; SIMULATION;

FAULT TOLERANT CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0032316474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)