A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 12, 1998, Pages 2042-2053

  Galton, Ian ^a,c,d,e   Huff, William ^a,f,g   Carbone, Paolo ^b,h,i   Siragusa, Eric ^a,e,j  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF PERUGIA   (Italy)

^c BROWN UNIVERSITY   (United States)

^d CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

^g Lear Astronics   (United States)

^h UNIVERSITY OF PADOVA   (Italy)

ⁱ ROMA TRE UNIVERSITY   (Italy)

^j NEWPORT CORPORATION   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DEMODULATION; FREQUENCY MODULATION; PHASE LOCKED LOOPS; SIGNAL TO NOISE RATIO;

DISTORTION RATIO; FREQUENCY TO DIGITAL CONVERSION; SPURIOUS FREE DYNAMIC RANGE;

DELTA SIGMA MODULATION;

EID: 0032316105     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.735546     Document Type: Article

References (16)

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