Designing a testable System on a Chip

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 2-7

  Kosonocky, S V ^a   Bright, A ^a   Warren, K ^a   Haring, R A ^a   Klepner, S ^a   Asaad, S ^a   Basavaiah, S ^a   Havreluk, B ^a   Heidel, D ^a   Immediato, M ^a   Jenkins, K ^a   Joshi, R ^a   Parker, B ^a   Rajeevakumar, T V ^a   Stawiasz, K ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL CIRCUITS; DIGITAL TO ANALOG CONVERSION; DYNAMIC RANDOM ACCESS STORAGE; LOGIC CIRCUITS;

TESTABLE SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 0032315484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)