Automatic insertion of scan structures to enhance testability of embedded memories, cores and chips

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 98-103

  Zarrineh, K ^a   Upadhyaya, Sh J ^a   Shephard, Ph ^a  

^a UNIVERSITY AT BUFFALO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; MAGNETIC CORES; MICROPROCESSOR CHIPS;

EMBEDDED CORES;

VLSI CIRCUITS;

EID: 0032312870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)