Gate oxide integrity testing on SOI wafers without test structure fabrication

IEEE International SOI Conference

Volumn , Issue , 1998, Pages 87-88

  Henaux, S ^a   Mondon, F ^a   Reimbold, G ^a   Moriceau, H ^a   Barge, T ^a   Auberton Herve, A J ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN OF SOLIDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR GROWTH; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; STATISTICAL TESTS;

GATE OXIDE INTEGRITY (GOI) TESTING;

SEMICONDUCTOR DEVICE TESTING;

EID: 0032311577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)