3-D simulation analysis of high performance SOI lateral BJT for RF applications

IEEE International SOI Conference

Volumn , Issue , 1998, Pages 29-30

  Kawanaka, Shigeru ^a   Fuse, Tsuneaki ^a   Inoh, Kazumi ^a   Shino, Tomoaki ^a   Nii, Hideaki ^a   Yamada, Takashi ^a   Yoshimi, Makoto ^a   Watanabe, Shigeyoshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER SIMULATION; ELECTRIC CONTACTS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SINGLE CRYSTALS;

BIPOLAR JUNCTION TRANSISTORS (BJT);

BIPOLAR TRANSISTORS;

EID: 0032307586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)