Implications of gate stack scaling in sub-100nm CMOS speed and reliability

Annual Device Research Conference Digest

Volumn , Issue , 1998, Pages 16-17

  Yeap, Geoffrey C F ^a   Krishnan, Srinath ^a   Yu, Bin ^a   Xiang, Qi ^a   Lin, Ming Ren ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC FIELDS; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; MATHEMATICAL MODELS; OXIDES; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

DIRECT TUNNELING; FRINGING INDUCED BARRIER LOWERING; GATE STACK SCALING; POLY DEPLETION;

MOSFET DEVICES;

EID: 0032307287     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)