Almost full-scan BIST solution - higher fault coverage and shorter test application time

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 1065-1073

  Tsai, Huan Chih ^a   Bhawmik, Sudipta ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING;

FULL-SCAN BUILT-IN SELF TEST (BIST) ARCHITECTURES;

BUILT-IN SELF TEST;

EID: 0032306251     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)