Enhancing topological ATPG with high-level information and symbolic techniques

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 504-508

  Corno, Fulvio ^a   Patel, Janak H ^a   Rudnick, Elizabeth M ^a   Sonza Reorda, Matteo ^a   Vietti, Roberto ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ERROR CORRECTION; FINITE AUTOMATA; STATE SPACE METHODS;

AUTOMATIC TEST PATTERN GENERATION; HIGH LEVEL INFORMATION; SYMBOLIC TECHNIQUES;

SEQUENTIAL CIRCUITS;

EID: 0032305245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)