Optimizing the instruction cache performance of the operating system

IEEE Transactions on Computers

Volumn 47, Issue 12, 1998, Pages 1363-1381

  Torrellas, Josep ^a,b   Xia, Chun ^c   Daigle, Russell L ^d  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

^c BrightInfo ^*

^d HEWLETT PACKARD COMPANY   (United States)

Author keywords

Cache miss rates; Code layout optimization; Instruction caches

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER OPERATING SYSTEMS; MATHEMATICAL MODELS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS);

CACHE MISS RATES; INSTRUCTION CACHES;

BUFFER STORAGE;

EID: 0032304622     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.737683     Document Type: Article

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