Comparative analysis of latches and flip-flops for high-performance systems

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 264-269

  Stojanovic, Vladimir ^a   Oklobdzija, Vojin ^a   Bajwa, Raminder ^a  

^a UNIVERSITY OF BELGRADE   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; LOGIC DESIGN; OPTIMIZATION; TIMING CIRCUITS;

INTERNAL CLOCK PROCESSING; POWER CONSUMPTION;

FLIP FLOP CIRCUITS;

EID: 0032303539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)