Incorporating timing constraints in the efficient memory model for symbolic ternary simulation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 400-406

  Velev, Miroslav N ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DELAY CIRCUITS; DIGITAL CIRCUITS; ERROR DETECTION; TIMING CIRCUITS;

EFFICIENT MEMORY MODEL; SYMBOLIC TERNARY SIMULATION; TIMING CONSTRAINT;

CONSTRAINT THEORY;

EID: 0032298325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)