Low-power design of a 64-tap, 4-bit digital matched filter using systolic array architecture and CVSL circuit techniques in CMOS

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 1998, Pages 1066-1069

  Yalcin, Tolga ^a   Ismailoglu, Neslin ^a  

^a SCIENTIFIC AND TECHNOLOGICAL RESEARCH COUNCIL OF TURKEY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIRECT SEQUENCE SYSTEMS; LOGIC CIRCUITS; SYSTOLIC ARRAYS;

CASCODE VOLTAGE SWITCH LOGIC (CVSL) CIRCUITS; DIGITAL MATCHED FILTERS (DMF);

DIGITAL FILTERS;

EID: 0032285013     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)