Design techniques for highly efficient class-F amplifiers driven by low voltage supplies

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 201-204

  Pedro, Jose Carlos ^a   Gomes, Luis Ramos ^a   Carvalho, Nuno Borges ^a  

^a UNIVERSITY OF AVEIRO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

HARMONIC LOAD IMPEDANCE TERMINATIONS; CLASS F POWER AMPLIFIER; CONDUCTION ANGLE; DESIGN TECHNIQUE; LOW VOLTAGE POWER SUPPLY; MICROWAVE POWER AMPLIFIER; OPERATING CONDITION; OPTIMUM PARAMETER SET; POWER AMPLIFIER DESIGNS;

ELECTRIC IMPEDANCE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; MICROWAVE AMPLIFIERS; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; OPTIMIZATION; SEMICONDUCTING GALLIUM ARSENIDE; VOLTAGE CONTROL; MICROWAVE INTEGRATED CIRCUITS;

POWER AMPLIFIERS;

EID: 0032282220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)

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6. S. Cripps, "A Theory for the Prediction of GaAs FET Load-Pull Power Contours", IEEE 1983 Intern. MTT Symposium Digest, pp.221-223, Boston, May, 1983.
7. H. Statz, P. Newman, I. Smith, R. Pucel and H. Haus, "GaAs FET Device and Circuit Simulation in SPICE", IEEE Trans, on Electron evices, vol. ED-34, pp. 160-169, Feb. 1987.