Embedded DRAM technology compatible to the 0.13 μm high-speed logics by using Ru pillars in cell capacitors and peripheral vias

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 1029-1030

  Nakamura, S ^a   Kosugi, M ^a   Shido, H ^a   Kosemura, K ^a   Satoh, A ^a   Minakata, H ^a   Tsunoda, H ^a   Kobayashi, M ^a   Kurahashi, T ^a   Hatada, A ^a   Suzuki, R ^a   Fukuda, M ^a   Kimura, T ^a   Nakabayashi, M ^a   Kojima, M ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ASPECT RATIO; CAPACITORS; CHEMICAL VAPOR DEPOSITION; ELECTRIC RESISTANCE; EMBEDDED SYSTEMS; ETCHING; GATES (TRANSISTOR); LOGIC CIRCUITS; RUTHENIUM; SILICON; SPUTTERING;

RUTHENIUM PILLAR TECHNOLOGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032279151     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)