Very-Long Instruction Word Digital Signal Processor based on the Logarithmic Number System

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 59-62

  Paliouras, V ^a   Karagiannis, J ^a   Aggouras, G ^a   Stouraitis, T ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

LOGARITHMIC NUMBER SYSTEMS (LNS); VERY-LONG INSTRUCTION WORD DIGITAL SIGNAL PROCESSOR; APPLICATION SOFTWARES; CONTROL HARDWARES; DIGITAL SIGNAL PROCESSING ALGORITHMS; FIR AND IIR FILTERS; IEEE-754 STANDARD; LOGARITHMIC NUMBER SYSTEM; VERY LONG INSTRUCTION WORDS; VLSI IMPLEMENTATION;

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; CODES (STANDARDS); COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; FIR FILTERS; IIR FILTERS; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); VLSI CIRCUITS; APPLICATION PROGRAMS; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; NUMBER THEORY; NUMBERING SYSTEMS; SIGNAL PROCESSING;

DIGITAL SIGNAL PROCESSING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0032276639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

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