Efficient implementation of multiplier-free decimation filters for ΣΔ A/D conversion

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1998, Pages 145-148

  Brambilla, Marco ^a   Liberali, Valentino ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; DELTA SIGMA MODULATION; ELECTRIC NETWORK SYNTHESIS; MULTIPLYING CIRCUITS;

A/D CONVERSION; AREA REQUIREMENT; DECIMATION FILTER; DESIGN TECHNIQUE; EFFICIENT IMPLEMENTATION; POWER-OF-TWO; SIGMA-DELTA; SIGMA-DELTA CONVERTERS;

ANALOG TO DIGITAL CONVERSION; FIR FILTERS;

MULTIPLIER-FREE DECIMATION FILTERS;

EID: 0032276634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.814851     Document Type: Conference Paper

References (8)

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