Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF IC's

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 949-952

  Tseng, Ying Che ^a   Huang, W Margaret ^a   Mendicino, Michael ^a   Ngo, David ^a   Ilderem, Vida ^a   Woo, Jason C S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC);

CMOS INTEGRATED CIRCUITS;

EID: 0032276256     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)