Low-cost neuroprocessor board for emulating the SOFM neural model

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 297-300

  Martin del Brio, Bonifacio ^a   Medrano Marques, Nicolas ^a   Hernandez Sanchez, Sergio ^a  

^a UNIVERSITY OF ZARAGOZA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

NEUROPROCESSOR BOARDS; SELF-ORGANIZING FEATURE MAPS (SOFM); DESIGN AND IMPLEMENTATIONS; LOW COSTS; NEURAL MODELING; NEUROPROCESSOR; PC BOARDS; PROGRAMMABLE LOGIC DEVICE;

COMPUTER SIMULATION; COST EFFECTIVENESS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DEVICES; MULTIPROCESSING SYSTEMS; CONFORMAL MAPPING;

NEURAL NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 0032273530     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)

1. S. Hay kin. Neural Networks, a Comprehensive Foundation. MacMillan-Prentice Hall, 1994.
2. B. Martín-del-Brío and A. Sanz Neural Networks and Fuzzy Systems, Theory and Practice. RA-MA Press, Madrid, 1997 (in Spanish).
3. B. Martín-del-Brío. "A dot product neuron for hardware implementation of competitive networks". IEEE Trans, on Neural Networks, 7, 529-532, 1996.
4. B. Martín-del-Brío, J. Blasco. "Hardware-oriented models for VLSI implementation of Self-Organizing Maps". Proc. Int. Workshop on ANN (IWANN95), Málaga (Spain). Springer, 1995.
5. Xilinx. The programmable logic databook. 1996.
6. C.E. Cox, W. Ekkerhard. "GANGLION, a fast FPGA implementation of a connectionist classifier". IEEE J. of Solid-State Circuits, 27, 288-299, 1992.