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Volumn 1, Issue , 1998, Pages 401-404

High speed multi-channel data acquisition chip

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; COMPARATORS (OPTICAL); COUPLED CIRCUITS; DATA ACQUISITION; DESIGN; DIGITAL CIRCUITS; GALLIUM ARSENIDE; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; PRINTED CIRCUIT DESIGN; SEMICONDUCTING GALLIUM; ELECTRIC NETWORK SYNTHESIS; LOGIC CIRCUITS; LOGIC DESIGN; MESFET DEVICES; SEMICONDUCTING GALLIUM ARSENIDE;

EID: 0032262082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.813349     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 1
    • 1842759179 scopus 로고
    • A 10-bit 5 msamples/sec CMOS 2-step flash ADC
    • Doemberg, J., and Hodges, D. A., "A 10-bit 5 Msamples/sec CMOS 2-step flash ADC", Conf. Proc. IEEE Custom IC, pp 18.6.6-18.6.4, 1988.
    • (1988) Conf. Proc. IEEE Custom IC , pp. 1866-1874
    • Doemberg, J.1    Hodges, D.A.2
  • 2
    • 0025462306 scopus 로고
    • New design technique for two step flash A/D converters
    • Ahmed, R. E., "New design technique for two step flash A/D converters", Electronics Lett., vol 26, no. 15, pp 1185-1186, 1990.
    • (1990) Electronics Lett. , vol.26 , Issue.15 , pp. 1185-1186
    • Ahmed, R.E.1
  • 4
    • 1842658031 scopus 로고
    • The simulation and performance of source coupled GaAs MESFET circuits
    • Singh, J., and Malyniak, R., "The simulation and performance of source coupled GaAs MESFET circuits", Conf. Proc. Modelling & Simulation, pp 259-266, 1993.
    • (1993) Conf. Proc. Modelling & Simulation , pp. 259-266
    • Singh, J.1    Malyniak, R.2
  • 5
    • 1842712168 scopus 로고
    • GaAs MESFET digital circuit techniques
    • Singh, J., and Malyniak, R.", GaAs MESFET digital circuit techniques", Proc. IEEE/ISIC Conf., pp 233-237, 1995.
    • (1995) Proc. IEEE/ISIC Conf. , pp. 233-237
    • Singh, J.1    Malyniak, R.2
  • 6
    • 1842758658 scopus 로고
    • GaAs design methodology and performance estimates for very high speed circuits using normally-off class of logic
    • Eshraghian, K., et al, "GaAs design methodology and performance estimates for very high speed circuits using normally-off class of logic", Proc. IREE/IEAust. conf., pp 227-232, 1993.
    • (1993) Proc. IREE/IEAust. Conf. , pp. 227-232
    • Eshraghian, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.