Timing analysis using Propositional Satisfiability

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 1998, Pages 95-98

  Guerra e Silva, Luis ^a   Marques Silva, Joao P ^a   Silveira, Luis Miguel ^a   Sakallah, Karem A ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

PROPOSITIONAL SATISFIABILITY-BASED ALGORITHMS; TIMING ANALYSIS; CIRCUIT DELAYS; COMPLEX PROBLEMS; FALSE PATHS; PATH DELAY; PROPOSITIONAL SATISFIABILITY;

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; PROBLEM SOLVING; SEQUENTIAL CIRCUITS; FORMAL LOGIC;

ELECTRIC NETWORK ANALYSIS; TIMING CIRCUITS;

EID: 0032260483     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)

1. P. Ashar, S. Malik and S. Rothweiler, "Functional Timing Analysis using ATPG," in Proceedings of the European Design Automation Conference, 1993.
2. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo and F. Somenzi, "Algebraic Decision Diagrams and Their Applications," in Proceedings of the International Conference on Computer-Aided Design, November 1993.
3. F. Brglez and H. Fujiwara, "A Neutral List of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," in Proceedings of the International Symposium on Circuits and Sys-tems(ISCAS), 1985.
4. H.-C. Chen and D. H. Du, "Path Sensitization in Critical Path Problem," IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 196-207, February 1993.
5. S. Devadas, K. Keutzer and S. Malik, "Computation of Floating-Mode Delay in Combinational Circuits: Practice and Implementation," IEEE Transactions on Computer-Aided Design, vol. 12, no. 12, pp. 1924-1936, December 1993.
6. T. Larrabee, Efficient Generation of Test Patterns Using Boolean Satisfiability, Ph.D. Dissertation, Computer Science Dept., Stanford University, STAN-CS-90-1302, February 1990.
7. P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and its Implications, Kluwer Academic Publishers, 1991.
8. P. McGeer, A. Saldanha, P. R. Stephan, R. K. Brayton and A. L. Sangiovanni-Vincentelli, "Timing Analysis and Delay-Test Generation Using Path Recursive Functions," in Proceedings of the International Conference on Computer-Aided Design, November 1991.
9. P. McGeer, A. Saldanha, R. K. Brayton and A. L. Sangiovanni-Vincentelli, "Delay Models and Exact Timing Analysis," in. Logic Synthesis and Optimization, T. Sasao (Ed.), 1993.
10. J. P. M. Silva and K. A. Sakallah, "Efficient and Robust Test-Generation Based Timing Analysis," in Proceedings of the International Symposium on Circuits and Systems (ISCAS), May 1994.
11. J. P. M. Silva and K. A. Sakallah, "GRASP-A New Search Algorithm for Satisfiability," in Proceedings of the International Conference on Computer-Aided Design, November 1996.
12. L. G. Silva, J. P. M. Silva, L. M. Silveira and K. A. Sakallah, "Realistic Delay Modeling in Satisfiability-Based Timing Analysis," to appear in the Proceedings of the International Symposium on Circuits and Systems (ISCAS), May 1998.