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Volumn 5, Issue , 1998, Pages 2905-2911
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Low-cost architecture for the implementation of worst-case-fair schedulers in ATM switches
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CONGESTION CONTROL (COMMUNICATION);
SWITCHING NETWORKS;
TELECOMMUNICATION TRAFFIC;
GENERALIZED PROCESSOR SHARING (GPS) POLICY;
WORST-CASE-FAIR SCHEDULERS;
ASYNCHRONOUS TRANSFER MODE;
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EID: 0032258088
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Article |
Times cited : (5)
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References (15)
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