Best combination of aluminum and copper interconnects for a high performance 0.18 μm CMOS logic device

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 829-832

  Igarashi, M ^a   Harada, A ^a   Amishiro, H ^a   Kawashima, H ^a   Morimoto, N ^a   Kusumi, Y ^a   Saito, T ^a   Ohsaki, A ^a   Mori, T ^a   Fukada, T ^a   Toyoda, Y ^a   Higashitani, K ^a   Arima, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; INTEGRATED CIRCUIT LAYOUT; LOGIC DEVICES;

DUAL DAMASCENE PROCESS;

CMOS INTEGRATED CIRCUITS;

EID: 0032257712     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)