Impact of crosstalk on delay time and a hierarchy of interconnects

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 291-294

  Yamashita, Kyoji ^a   Odanaka, Shinji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; ELECTRIC RESISTANCE;

MULTILEVEL INTERCONNECT SCHEMES;

INTEGRATED CIRCUITS;

EID: 0032254713     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)