Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

IEE Proceedings: Circuits, Devices and Systems

Volumn 145, Issue 6, 1998, Pages 402-408

  Bisdounis, L ^a,b   Koufopavlou, O ^a,b   Nikolaidis, S ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

CMOS inverters; Submicron technology

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; SHORT CIRCUIT CURRENTS; WAVEFORM ANALYSIS;

COUPLING CAPACITANCE; PROPAGATION DELAY; SUBMICRON TECHNOLOGY;

ELECTRIC INVERTERS;

EID: 0032228812     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19982391     Document Type: Article

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